1. Field of the Invention
The present invention relates generally to load boards, and more specifically to a circuit integrated into a load board for performing high resolution quiescent current measurements of a CMOS integrated circuit (IC) device under test (DUT).
2. Related Art
In an engineering environment, it is important to be able to test a prototype electronic device (known as the DUT), such as a processor chip, before it is sent out to mass manufactured. A load board allows power supply and logic pins of the DUT to be connected to an IC tester for reliability testing of the DUT.
A short coming with current load board designs is that they occasionally need custom designed test circuits for increasing performance or enhancing test coverage. It usually includes adding interconnect or altering existing interconnect between the DUT, IC tester and corresponding power systems. Consequently, it is necessary to build particular test circuits from scratch for each new implementation of a DUT. This involves placing test circuit components on the surface of the load board in relation to the DUT, and wiring in the desired interconnect changes, creating an opportunity for wiring mistakes and shorts or opens.
Furthermore, due to the varying size, pin outputs, and nature of DUTs, it is often time consuming to design custom test circuits to connect IC testers to the DUT on the load board. Another problem associated with current load board designs, is that quite often, it is not possible to place the test circuit in optimal relation to the DUT. As a result, long inductive connections and unshielded interconnections are prevalent. This often compromises the integrity of the test circuit and test results.
Therefore, what is needed, is a generic test circuit capable of functioning with varying DUTs that can be easily manufactured with the load board and requires little to no wiring. A test circuit that is designed to be located in a fixed and optimal position on the load board is also needed.